CIS=CT32BN_CAP0, CTM=TIMER_MODE_EVERY_RI
Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
| CTM | Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge 0 (TIMER_MODE_EVERY_RI): Timer Mode: every rising PCLK edge 1 (RISING): Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 2 (FALLLING): Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 3 (BOTHEDGES): Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. |
| CIS | Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking: 0 (CT32BN_CAP0): CT32Bn_CAP0 |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |